53A-457 – MIL·STD-1553A/B Intelligent Bus Monitor Card
OPT 1V – Add VXIbus Compatibility
53A-782 – Hooded Connector

• Real-time data acquisition
• 65,000 word memory buffer
• User-definable capture criteria for data reduction
• 32-bit Time-Tag for data-logging
• High-speed parallel port to off load to an external device for auxiliary communications
• Acts as 1553 monitor and/or analyzer

The complete implementation of many MIL-STD-1553 testing applications requires that the user be able to monitor and analyze both 1553 data bus traffic flow and data content. The 53A-457 Intelligent Bus Monitor Card was designed to give the user a sophisticated tool that fulfills this requirement. At the heart of the 53A-457 is a powerful Bus Monitor that allows 1553 data and its associated characteristics to be captured and transferred to the system controller in real time;  i.e., the transfer of buffered test data to the system controller can occur at the same time as data capture without interrupting or slowing the flow of new data capture.

The 53A-457’s data capture ability is combined with a “Bus Analyzer” capability that enables the user to define and control the timing and content of data to be captured. Up to 65,000 1553 data words can be captured and stored in the 53A-457’s on-card high-speed buffer memory. By defining specific data transmissions and/or words preceding the data of interest, as well as the actual bits and words associated with that data. the user has the ability to select the exact data to be captured. Data capture ability is further expanded by the user’s ability to define multiple IF-THEN-ELSE conditions when selecting exact data sequences to be captured. To insure the 53A-457’s ability to make real time data capture decisions under all conditions, IF-THEN-ElSE conditions are implemented with a unique reprogrammable hardware design rather than a microprocessor and software.

The 53A-457 identifies each 1553 word as a Command, Status, or Data word. Any associated message and/or word errors are included as part of the information stored with all captured data. Message formats such as Mode Commands. RT-to-RT transfers. Broadcast and Superseding commands can be defined for each capture sequence. Any or all of the above identifiers can be used with the IF-THEN-ElSE constraints to define data capture conditions.

The Card associates a 32-bit time-tag with each Command and/or Status word captured. This 32-bit time tag utilizes a continuous counter which is reset to zero at power-up or under program control. The time-tag resolution may be programmed as 1/2, 1, 10 or 20 microseconds. Both the time-tag clock and a time-tag clock reset are available at the front edge connector for use by multiple 53A-457’s or other instruments in the test system. Routing a common time-tag clock between multiple 53A-457’s allows 1553 data occurring on redundant buses to be easily time correlated. Time-tagging can be suspended under program control to increase both data storage capability and the transfer rate of data to the system controller.

When considering real time data capture strategies, it is important to understand that continuous real time data capture occurs only when the system controller can continuously accept data from its test equipment interface bus at a rate exceeding the effective rate of data capture from the 1553 bus. In many testing applications, this is not possible. To facilitate continuous data capture, an additional 8-bit parallel, high-speed interface port is provided at the front card edge of the 53A-457. This interface can be configured either with a handshake hold off for data flow control or with a free running output and data available strobe. The port could be used to directly drive the DMA channel of a host computer or output data to a digital tape recorder or a logic analyzer. The maximum output rate of the port is 1 Megabyte per second.

The 53A-457 is programmed by means of ASCII characters sent to the CDSbus System from the system controller. Both 1553 data used for defining data capture sequences and 1553 measurement data are transferred between the system controller and the 53A-457 using 8-bit binary data bytes to improve test equipment to system controller data throughput.

Embedded self test firmware, along with eight LEDs, provide Built-In-Test Equipment (“BITE”) for the 53A-457. The LEDs indicate acquisition mode, receiver active, data stored, trigger occurred, capture sequence progress and received errors.

MIL-STD-1553 Bus Monitor.

Message Capability:
Up to 65,300 words of captured data may be stored. Captured data may be input by the system controller at the same rate it is occurring or faster (up to 1 Megabyte/second) without affecting additional data capture.

Receiver Error Checking:
Message Basis, word count, mode command format, unused mode codes, broadcast command format, RT-to-RT addresses not different, RT response time.
Word Basis, bit transition time errors, parity errors, dropped bit errors, sync pattern errors, gap before data words error.

Receiver Error Mask:
RT response time error may be programmed between 4.5 and 13.5 microseconds.

IF-THEN-ELSE Programming:
Up to ten IF-THEN-ELSE conditions may be programmed to define data capture, error content, triggering and system interrupts. Up to ten 1553A/B data trigger words may be programmed as to data or error content. Data capture can be programmed to occur after from 1 to 31 occurrences of one or more IF-THEN-ELSE conditions. Default programming captures any 1553A/B activity; any predefined 1553 command status or data word may be used to control data capture activity.

1553 Bus Coupling:
Direct Coupling, 1 : 1 turns ratio, 55 Ohm isolation resistor each leg.
Transformer Stub Coupling, 1:1.41 turns ratio.

1553 Analog Input
Maximum Input, 40V PTP, transformer coupled.
Threshold, programmable from 0.6V PTP to 6.50V PTP in 0.025V PTP increments.

Auxiliary Inputs (TTL):
External Trigger: External Halt,  Data Acknowledge, Redundant Receiver Active, Time-Tag Clock,
Time-Tag Clock Reset.

Auxiliary Outputs (TTL):
Received Data, Receiver Clock, Received Sync, RT Status Error, Receiver Error: Bus Controller
Transmission, Time-Tag Clock, Buffer Full, Buffer Empty, Time-Tag Clock Reset.

Auxiliary Outputs (O.C):
IF-THEN-ELSE condition 0 through 5 active, Acquisition Mode Off, Receiver Active.

Time Base:
Internal, 16 MHz crystal oscillator.
External, TTL clock input for use in multi-card time-tag synchronization.

Interrupt Capability:
Card may be programmed to interrupt the system controller on any defined word match, IF-THEN-ELSE condition, buffer starts filling or becomes full, or if a 1553 error is detected.

Programmed By:
Single ASCII character or ASCII character followed by binary data bytes.

Recommended Cable:

Available Option:
OPT 1V, add VXIbus compatibility.