53A-424 FDAU RECEIVER CARD
53A-424 – FDAU Receiver Card
OPT 1V- Add VXIbus Compatibility
53A-780 – Hooded Connector
• Designed to test Flight Data Acquisition Units
• Receives either Harvard bi-phase or bi-polar RZ as specified by ARINC 717-3 and ARINC 573-7
• Multiple data rates under program control
• Single shot or continuous modes
The 53A-424 FDAU Receiver Card allows the user to receive and store the serial digital data generated by the Flight Data Acquisition Units on certain civil aircraft The Card can receive either Harvard bi-phase or bi-polar RZ (ARINC 429) encoded data as specified by ARINC 717-3 and ARINC 573-7.
The 53A-424 will receive and store up to eight major frames of 12-bit data words. Data words are reformatted into 8-bit bytes for transmission to the system controller. Data rates of 768, 1536, or 3072 bits per second can be handled under full program control.
The card operates in either single shot or continuous mode. In single shot. the next eight major frames received after the trigger command are stored. In continuous mode, the last eight major frames received are continuously stored in circular memory.
A built-in test pattern generator for both Harvard bi-phase and bi-polar RZ is included.
13 LEDs provide Built-In-Test Equipment (“BITE”) for the FR Card. All phases of operation are monitored and the results continuously displayed to allow the user to determine operational status and to quickly diagnose any test procedure problems.
Single receiver either Harvard bi-phase or bi-polar RZ input per ARINC 573 and 717.
Connects directly to digital outputs on FDAU.
Programmable at 768, 1,536, or 3,072 bits per second.
Two Programmable Modes:
Single Shot Mode, captures eight frames of input data from FDAU.
Continuous Mode, continuously captures last eight frames of data from FDAU.
Four FDAU sync words are program selectable, with the first bit received being either MSB or LSB.
Storage for 2,048 12-bit data words.
Data Returned to System Controller:
Format two 8-bit bytes per 12-bit FDAU word.
Transfer Rate, 10,000 bytes/second maximum with actual rate determined by the system controller.
Output Signals (generated from FDAU data):
Reconstructed Harvard bi-phase and bi-polar RZ data in TTL, low true, NRZ format.
Reconstructed Harvard bi-phase and bi-polar RZ clocks, TTL.
Subframe sync/separate output line for each subframe, TTL, low true, pulse, µsec wide during first bit of word following sync word.
Data Comparison Output, TTL, low true. True w hen Harvard bi-phase and bi-polar RZ data are equal.
Test Generator Output
Continuously outputs a fixed major frame of Harvard bi-phase and bi-polar RZ data. Sync words are LSB first
OPT 1V, add VXIbus compatibility.