53A-530

BIT ERROR RATE TESTING
The 53A-530 BERT and 53A-531 BERR FORMAT CONVERSION Cards are useful in applications which require programmable bit error rate testing. These applications include: Telecommunications Industry – testing the integrity of ground and satellite communications channels and equipment such as multiplexers, demultiplexers, digital radios, modems, etc.; Digital Computer Industry- testing magnetic tape drives, disc drives, etc.

The BERT and BERR Cards were designed to allow the user to, under program control, measure both “bit error’ and “peak block-error rate.” These measurements can be made irrespective of the transmission media path delay.

Under program control, the user can change the block size and introduce phase offset and phase jitter on the clock and data. Bit rates are programmable up to 10 Mb/s synchronous operation. Inputs are provided to allow the user to inject a specific number of errors into the system.

Eight programmable data formats are available:
NRZ, also known as “Polar NRZ and NRZ-L.”
RZ, also known as “Bipolar RZ.”
Alternate Mark Inversion (AMI), also known as “Bipolar.”
Diphase, also known as “Manchester.”
Conditioned NRZ, also known as “NRZ-M.”
Conditioned RZ.
Conditioned Bipolar:
Conditioned Diphase.

The wide range of formats and adjustable differential inputs and outputs ensure that the system will meet both present and future testing requirements without having to build external format conversion devices.

FORMAT CONVERSION
Since the BERT Card can receive NRZ data as well as transmit any format and the BERR Card can transmit NRZ data as well as receive any format the two cards connected as shown in the diagram below can be used to convert from one data format to another – e.g., AMI to Manchester:

**Note: Clock must be same frequency as data.

ERROR AND DISTORTION INJECTION
The diagram above can be used not only to reformat the data but also to programmatically distort (phase offset and jitter) the data and clock of a system. In addition, through inputs provided on the BERT Card. data errors may be injected into the data stream.

53A-530 BIT ERROR RATE TRANSMITTER (BERT) CARD

ORDERING INFORMATION
53A·530 – Bit Error Rate Transmitter (BERT) Card
OPT 1V – Add VXlbus Compatibility
53A-780 – Hooded Connector

• Programmable output data format and output data pattern
• Programmable data distortion
• May be operated as a transmitter only or as a receiver/retransmitter
• Synchronous data rates up to 10 Mb/s
• Asynchronous data rates up to 1.55 Mb/s

The BERT Card can transmit an internally generated sequence, or retransmit externally supplied NRZ data. The user may inject programmable phase jitter or phase offset, at programmable data rates up to 10 Mb/s. The BERT Card has eight programmable data formats. Inputs are provided to allow the user to inject a specific number of data errors into the transmitted data.

BITE
Three LEDs provide the Built-In-Test Equipment (“BITE”) for the BERT Card. These LEDs will be lit when data is being transmitted, if the BERT Card is programmed to distort the data or data clock with phase jitter or phase offset, and if the external error injection input is enabled.

Specifications
Mode /programmable):
Transmitter or Receiver/Transmitter.
Synchronous or Asynchronous.

Data Rates /programmable):
Programmable with a resolution of 4 decimal digits.

Maximum Data Rate:
Synchronous, 10 Mb/s.
Asynchronous, 1.55 Mb/s.

Types of Output Data Formats (programmable, conditioned or not):
RZ.
NRZ.
AMI /Bipolar).
Diphase.
Manchester.

Types of Generated Data Patterns (programmable):
External Data Input.
All 0s or All 1s.
Alternate 0s and 1s.
Pseudo Random Binary Sequence (PRBS).
Inverted PRBS.
7, 9, 11 or 15 bit 2^n-1 sequence, (switch-selectable).

Data Distortion (programmable):
Data will lead or follow clock by 12.5% or 25%.
Jitter clock or data by 12.5% or 25%.
Jitter clock and data by 12.5%.
Clock and data 180° out of phase.

Note: Above 3.00 Mb/s no distortion may be programmed. Above 1.55 Mb/s only 25% distortion may be programmed.

Receivers for Input Data and Clock:
Differential Input Impedance, 12 KOhm.
Single-ended Input Impedance, 6 KOhm.
Maximum Differential Voltage, ±60 volts.
Maximum Common Mode Voltage, ±30 volts.
High, greater than 0.5 volts.
Low, less than 0.04 volts. With supplied adjustable (-15 to +15) reference voltage these inputs can be single-ended.

Oscillator (internal):
24.8 MHz oscillator .005%. ±1 x 10^-6/ yr. standard.
Any frequency between 10 MHz and 26 MHz is available on request.

Drivers for Output Data and Clock:
Maximum Differential Output, 8.0 volts.
Each leg independently adjustable between 0 and ±4. OV
Output Impedance, 10 Ohm (nominal).
Output Current 50 mA (maximum).
Differential Offset, less than 50 mV
Common Mode Offset, less than 200 mV
Short circuit protected.
Output Slew 100V/µsec, at rated output.
Output Ringing, less than 10% overshoot or undershoot into 78 Ohm load.

Output Timing When Using Internal Clock and Data Sources:
Duty Cycle 50%, ±2%.
Jitter, <±2% of a nominal data unit interval.
Phasing Between Data Clock and Data, <±4% of a nominal data unit interval.

Programmed By:
ASCII Characters.

Recommended Cable:
53A-780.

Available Option:
OPT 1V, add VXIbus compatibility.