53A-412 PROGRAMMABLE DIGITAL I/O CARD
53A-412 – Programmable Digital I/O Card
OPT 01 – Optical Isolation
OPT 02 – Open Collector I/O
53A-782 · Hooded Connector
• 48 TTL/CMOS compatible digital I/O lines
• Programmable as inputs or outputs on a byte basis
• 6K buffered memory
• Data output controllable on a bit, byte, or group of bytes basis
• Extensive self test
• Message based instrument
The 53A-412 Programmable Digital I/O Card provides 48 TTL and CMOS compatible, bidirectional digital I/O lines. For programming convenience, and to help in defining proper test flow, these 48 programmable I/O signal lines are organized as six 8-bit bytes. Two available options further extend the usefulness of the Card by adding optical isolation or open collector capability to the I/O.
Each of the six bytes can be completely and independently configured under full program control. All commands and responses are normally in ASCII hex notation for ease of programming, and to insure compatibility with the widest range of systems controllers. However, a binary capability is also supplied standard for those applications requiring increased data transfer speed. Programmable parameters include:
• selection of any byte as either input or output
• definition of masks for input and output data
• I/O control on command basis, on external handshake, or on a programmable time count
• logic sense of input output and handshake lines
• full reporting of operating parameters at any time
Data output can be controlled as bits, as individual bytes, and/or as groups of bytes. Control of the output can be directly applied on a command basis, or further qualified and controlled by using external handshakes, or by means of a programmable time count.
Data input is also fully under program control. The card can report the state of all input bytes, groups of input and/or output bytes, and single bits of a byte. Input data can be updated on a command request basis, or on a qualified basis using external handshakes.
User-defined masks can be overlaid on the data prior to output. Masks may also be applied to individual input bytes before they are returned to the system controller to improve data post-processing speed and to promote ease of data interpretation.
The sense of inputs and outputs can be set to either active high or active low under program control. The active edge can also be programmed for handshake lines. All I/O lines are both TTL and CMOS compatible, with up to 24 mA of sink current provided for each output. With Option 01 installed, the I/O section of the card is fully isolated from system ground using opto-isolators and an isolated power supply contained on the card.
External control signals (handshake) are provided for output and input data control. Output data control signals are Ready For Data (RFD), Data Available (DAV), and External Tri-State control (ETS0-ETS5). Input data control signals are Data Ready (DRD) and Data Acknowledge (DAK).
A binary I/O mode is provided which allows a total of 6000 bytes to be allocated for buffered binary I/O through the card. Two modes are provided for binary input: Mode 1 inputs data as long as there is free memory in the buffer to accept it, while Mode 2 overwrites the oldest data in memory when the input buffer is filled. Binary input is controlled by the Data Ready handshake. Data can be simultaneously read from the input buffer while new data is being strobed in, dynamically freeing memory for additional input. The card can also be programmed to generate an interrupt when the input buffer is full.
Binary output can be controlled by either the Ready For Data handshake or on a programmable time basis from 100 µs to 858 seconds. Two modes are provided: Mode 1 outputs data as long as there is data in the output buffer. Mode 2 allows pre-loading the output buffer, then defining a ‘thread’ sequence to control how preloaded data is output. For Mode 1, data can simultaneously be loaded into the card while data is being output. The number of bytes left to be output can be read at any time, and the card programmed to generate an interrupt when the output buffer is empty. For Mode 2, an interrupt can be programmed to occur when a breakpoint occurs in the sequence.
The 53A-412 provides full access to system status information, which is especially helpful during system trouble-shooting, software debugging, and operational system checks. At any time, the system controller can read the state of the external handshake lines. the programmed I/O configuration, the programmed active edges of all handshake signals, which handshake signals are active, the programmed logic sense of each I/O byte, the tri-state condition of each output byte, and up-to-date error data.
Built-In-Test Equipment (“BITE”) is provided on the card by an internal loop-back path that allows the card to be tested with its outputs tri-stated, verifying I/O paths for each byte. A self test is automatically performed on power up, or it can also be commanded. Front panel LEDs indicate the error status, data handshake signals, current tri-state conditions, input/output configuration, and individual I/O bits. In addition, the Query and Operation commands can be used to determine the current state of the card during operation.
Number of I/O Channels: 48.
Configuration: I/O lines selectable as input or output on an 8-bit byte basis. Also tri-state programmable on an 8-bit byte basis.
Byte Transfer Polarity: All input and output bytes individually selectable as active high or active low.
Input Data: Returned as two hexadecimal ASCII characters per byte, or in binary.
Input Control: On program command or with external Data Ready and Data Acknowledge handshake.
Output Data: Programmed as two hexadecimal ASCII characters per byte, or on an individual bit basis or in binary.
Output Control: On program command, with external Ready for Data and Data Available handshake or on a programmable time count.
Tri-State Control: On program command on an individual byte, and by individual external tri-state control signals for each byte.
Mask Capability: On an individual byte basis, for input or output, AND, OR, and XOR (exclusive OR) masking provided.
Byte Ordering: A predefined sequence for input or output byte transfer may be programmed. Bytes may be transferred in any required order.
Interrupt Modes: Program selectable, on Ready For Data handshake, Data Ready handshake, Binary Input Buffer Full, Binary Output Buffer Empty.
External Control Logic Sense: Data Available, Ready For Data, Data Acknowledge, and Data Ready control line polarities are all individually program selectable as low or high true.
I/O Signal Type: TTL and CMOS compatible (Option 02, TTL open collector outputs).
Isolation Resistance: >100e6 Ohms at 500V dc (Option 01 only).
Isolation Voltage: >250V dc (Option 01 only).
External Control Lines: External Tri-state Input to Tri-state Active, typical, 30 nsec; maximum. 63 nsec.
Valid Output Data to Data
Available Strobe: 0 nsec.
Data Acknowledge to Data Ready Strobe Delay, 0 nsec.
Maximum Output Data Rate: Buffered binary data using either the internal trigger
or the RFD handshake:
10 KHz (1 to 3 output bytes).
8 KHz (4 to 6 output bytes).
ASCII Hex Data: 8KHz.
Maximum Input Data Rate: Buffered binary data using the DRD handshake: 5KHz.
Front Edge Signal Connector: 76-pin connector.
53A-782 Hooded Connector.
OPT 01, optical isolation.
OPT 02, open collector I/O.